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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MPC905/D
1:6 PCI Clock Generator/ Fanout Buffer
The MPC905 is a six output clock generation device targeted to provide the clocks required in a 3.3V or 5.0V PCI environment. The device operates from a 3.3V supply and can interface to either a TTL input or an external crystal. The inputs to the device can be driven with 5.0V when the VCC is at 3.3V. The outputs of the MPC905 meet all of the specifications of the PCI standard.
MPC905
* * * * * *
Six Low Skew Outputs Synchronous Output Enables for Power Management Low Voltage Operation XTAL Oscillator Interface 16-Lead SOIC Package 5.0V Tolerant Enable Inputs
1:6 PCI CLOCK GENERATOR/ FANOUT BUFFER
The MPC905 device is targeted for PCI bus or processor bus environments with up to 12 clock loads. Each of the six outputs on the 16 1 MPC905 can drive two series terminated 50 transmission lines. This capability effectively makes the MPC905 a 1:12 fanout buffer. D SUFFIX The MPC905 offers two synchronous enable inputs to allow users PLASTIC SOIC PACKAGE flexibility in developing power management features for their designs. CASE 751B-05 Both enable signals are active HIGH inputs. A logic `0' on the Enable1 will pull outputs 0 to 4 into the logic `0' state. A logic `1' on the Enable1 input will result in outputs 0 to 4 to be toggling. A logic `0' on Enable2 will cause output BLK5 to a logic `0' state, whereas a logic `1' on Enable2 will cause output BLK5 to toggle. The oscillator remains on. The Enable2 input can be used to disable any high power device for system power savings during periods of inactivity. Both enable inputs are synchronized internal to the chip so that the output disabling will happen only when the outputs are already LOW. This feature guarantees no runt pulses will be generated during enabling and disabling.
VDD (3) GND (3)
Pinout: 16-Lead Plastic Package (Top View)
BCLK0 XTAL_OUT 1 XTAL_IN BCLK1 BCLK2 XTAL_OUT BCLK3 BCLK4 SYNCHRONIZE BCLK5 Enable2 SYNCHRONIZE Enable2 2 GND1 3 BCLK0 4 VDD1 5 Enable1 BCLK1 6 GND2 7 BCLK2 8 16 XTAL_IN 15 Enable1 14 BCLK5 13 VDD3 12 BCLK4 11 GND3 10 BCLK3 9 VDD2
01/01
(c) Motorola, Inc. 2001
1
REV 2
MPC905
PIN CONFIGURATIONS
Pin XTAL_IN, XTAL_OUT Enable1, Enable2 BCLK0 - BCLK5 VDD GND I/O Input Input Output Type Analog LVCMOS LVCMOS Supply Supply Function Crystal Oscillator Terminals Output Enable Clock Outputs Positive Power Supply Negative Power Supply
FUNCTION TABLE
ENABLE1 0 0 1 1 ENABLE2 0 1 0 1 Outputs 0 to 4 Low Low Toggling Toggling Output 5 Low Toggling Low Toggling OSC (On/Off) ON ON ON ON
ABSOLUTE MAXIMUM RATINGS*
Symbol VDD VIN Toper Tstg Tsol Tj ESD ILatch Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Soldering Temperature Range (10 Sec) Junction Temperature Range Static Discharge Voltage Latch Up Current 1500 50 Parameter Min -0.5 -0.5 0 -65 Max 4.6 VCC + 0.5 +70 +150 +260 +125 Unit V V C C C C V mA
* Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol TA VCC tDCin Parameter Ambient Temperature Range Positive Supply Voltage (Functional Range) Thigh (at XTAL_IN Input) Tlow (at XTAL_IN Input) Min 0 3.0 0.44T1 0.44T1 Max 70 3.6 0.56T1 0.56T1 Unit C V T = Period
1. When using External Source for reference, requirement to meet PCI clock duty cycle requirement on the output.
DC CHARACTERISTICS (TA = 0-70C; VDD = 3.3V 0.3V)
Symbol VIH VIL VOH VOL IIH IIL ICC Characteristic High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input High Current Input Low Current Power Supply Current DC 33MHz 66MHz XTAL_IN Others 20 37 78 2.4 0.4 2.52 2.5 45 95 9.0 4.5 Min 2.0 Typ Max 5.52 0.8 Unit V V V V A A A mA mA pF IOH = -36mA1 IOL = 36mA1 Condition
CIN
Input Capacitance
1. The MPC905 can drive 50W transmission lines on the incident edge. Each output drives one 50W parallel terminated transmission line to VTT = VCC/2. Alternately, the device drives up to two 50W series terminated transmission lines per output. 2. XTAL_IN input will sink up to 10mA when driven to 5.5V. There are no reliability concerns associated with the condition. Note that the Enable1 input must be a logic HIGH. Do not take the Enable1 input to a logic LOW with >VCC volts on the XTAL_IN input.
MOTOROLA
2
TIMING SOLUTIONS DL207 -- Rev 0
MPC905
AC CHARACTERISTICS (TA = 0-70C; VDD = 3.3V 0.3V)
Symbol Fmax tpw Characteristic Maximum Operating Frequency Output Pulse Width Using External Crystal Using External Clock Source HIGH (Above 2.0V) LOW (Below 0.8V) HIGH (Above 2.0V) LOW (Below 0.8V) Min - DC 0.40T1 0.40T1 0.45T2 0.45T2 T - 400ps Rising Edges Falling Edges 1 Enable1 Enable2 Enable1 Enable2 6 30 400 500 4 5 4 4 4 ps V/ns ms Cycles Cycles db Degrees Series Terminated Transmission Lines Typ Max 50 100 0.60T1 0.60T1 0.55T2 0.55T2 Unit MHz T = Periods Condition
tper tos tr, tf tEN tDIS Aosc Phase
Output Period Output-to-Output Skew Rise/Fall Times (Slew Rate) Enable Time Disable Time XTAL_IN to XTAL_OUT Oscillator Gain Loop Phase Shift Modulo 360 +
T = Desired Period
1. Assuming input duty cycle specs from Recommended Operationg Conditions table are met. 2. Assuming external crystal or 50% duty cycle external reference is used.
Pin 16
Pin 1
Pin 16
Pin 1
fFUND CTRAP
+
1 2p LTRAP CTRAP
Y1 33.3333MHz C1 10pF C3
100
Y1 11.1111MHz
LTRAP 16pF
16pF
C1
10pF
C3
Figure 1. Crystal Oscillator Interface (Fundamental)
Figure 2. Crystal Oscillator Interface (3rd Overtone)
Table 1. Crystal Specifications
Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Parallel Resonance* 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 100W 5ppm/Yr (First 3 Years)
TIMING SOLUTIONS DL207 -- Rev 0
3
MOTOROLA
MPC905
BCLK5
BCLK0-4
ENABLE2
ENABLE1
Figure 3. Enable Timing Diagram
APPLICATIONS INFORMATION
Driving Transmission Lines The MPC905 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of approximately 10 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions data book (DL207/D). In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC905 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC905 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC905 OUTPUT BUFFER IN 10 RS = 40 ZO = 50 OutA
MPC905 OUTPUT BUFFER IN 10W
RS = 40
ZO = 50 OutB0
RS = 40
ZO = 50 OutB1
Figure 4. Single versus Dual Transmission Lines The waveform plots of Figure 5 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC905 output buffers is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. The output waveform in Figure 5
MOTOROLA
4
TIMING SOLUTIONS DL207 -- Rev 0
MPC905
shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 40 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/55) = 1.36V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.73V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
3.0 OutA tD = 3.8956 10 OutB tD = 3.9386 RS = 30 ZO = 50
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC905 OUTPUT BUFFER
RS = 30
ZO = 50
2.5
VOLTAGE (V)
2.0 In 1.5
10 + 30 k 30 = 50 k 50 25 = 25 Figure 6. Optimized Dual Line Termination
1.0
0.5
0 2 4 6 8 TIME (nS) 10 12 14
Figure 5. Single versus Dual Waveforms
TIMING SOLUTIONS DL207 -- Rev 0
5
MOTOROLA
MPC905
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
MOTOROLA
6
TIMING SOLUTIONS DL207 -- Rev 0
MPC905
NOTES
TIMING SOLUTIONS DL207 -- Rev 0
7
MOTOROLA
MPC905
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MOTOROLA
8
TIMING SOLUTIONS MPC905/D DL207 -- Rev 0

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